SISA=B_0x0, CRCA=B_0x0, SFA=B_0x0, BOA=B_0x0
LTDC global configuration 2 register
| BLA | background layer ability (pixels of background layer are read from memory) |
| STSA | slave timings synchronization ability |
| DVA | dual-view ability |
| DPA | secondary RGB output port ability |
| BW | bus width (log2 of number of bytes) 2 (B_0x2): 32-bit bus 3 (B_0x3): 64-bit bus 4 (B_0x4): 128-bit bus |
| EDCA | external display control ability |
| OCA | output conversion ability (RGB to YCbCr) |
| AXIIDA | AXIID ability |
| ROTA | rotation support ability |
| SISA | second interrupt set ability 0 (B_0x0): second interrupt set not available 1 (B_0x1): second interrupt set available |
| SFA | single frame mode ability 0 (B_0x0): single frame not available 1 (B_0x1): single frame available |
| CRCA | CRC ability 0 (B_0x0): CRC no computation available 1 (B_0x1): CRC computation available |
| BOA | blending order ability 0 (B_0x0): blending order fixed 1 (B_0x1): blending order configurable |