stm32 /stm32n6 /STM32N645 /LTDC /LTDC_GCR

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Interpret as LTDC_GCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LTDCEN 0 (B_0x0)GAMEN 0DBW0DGW0DRW0 (B_0x0)DEN 0 (B_0x0)CRCEN 0 (B_0x0)SFEN 0 (B_0x0)SFSWTR 0 (B_0x0)PCPOL 0 (B_0x0)DEPOL 0 (B_0x0)VSPOL 0 (B_0x0)HSPOL

SFSWTR=B_0x0, LTDCEN=B_0x0, PCPOL=B_0x0, GAMEN=B_0x0, DEPOL=B_0x0, VSPOL=B_0x0, SFEN=B_0x0, DEN=B_0x0, HSPOL=B_0x0, CRCEN=B_0x0

Description

LTDC global control register

Fields

LTDCEN

LTDC global enable

0 (B_0x0): LTDC disabled

1 (B_0x1): LTDC enabled

GAMEN

Gamma correction enable

0 (B_0x0): Gamma correction disabled (pixels bypass the gamma operator)

1 (B_0x1): Gamma correction enabled

DBW

dither blue width

DGW

dither green width

DRW

dither red width

DEN

dither enable

0 (B_0x0): dither disabled

1 (B_0x1): dither enabled

CRCEN

CRC enable

0 (B_0x0): CRC disabled

1 (B_0x1): CRC enabled

SFEN

single-frame mode: mode enable

0 (B_0x0): single-frame disabled: a trigger (on SFSWTR) generates a continuous flow.

1 (B_0x1): single-frame enabled: a trigger (on SFSWTR) generates a single frame.

SFSWTR

single-frame mode: software trigger

0 (B_0x0): no action

1 (B_0x1): triggers one frame

PCPOL

pixel clock polarity

0 (B_0x0): the pixel and sync data are generated at the rising-edge of the output LCD_CLK clock.

1 (B_0x1): the pixel and sync data are generated at the falling-edge of the output LCD_CLK clock.

DEPOL

blanking (no data/pixel) polarity

0 (B_0x0): blanking (no data/pixel) polarity is active low.

1 (B_0x1): blanking (no data/pixel) polarity is active high.

VSPOL

vertical synchronization polarity

0 (B_0x0): vertical synchronization is active low.

1 (B_0x1): vertical synchronization is active high.

HSPOL

horizontal synchronization polarity

0 (B_0x0): horizontal synchronization polarity is active low.

1 (B_0x1): horizontal synchronization polarity is active high.

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