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stm32 /stm32n6 /STM32N645 /LTDC /LTDC_L1RCR

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Interpret as LTDC_L1RCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IMR 0 (B_0x0)VBR 0 (B_0x0)GRMSK

VBR=B_0x0, IMR=B_0x0, GRMSK=B_0x0

Description

LTDC layerx reload control register

Fields

IMR

immediate reload trigger

0 (B_0x0): no effect

1 (B_0x1): The shadow registers are reloaded immediately.
VBR

vertical blanking reload request

0 (B_0x0): no effect

1 (B_0x1): The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).
GRMSK

shadow reload control, global (centralized) reload masked

0 (B_0x0): global reload active for this layer (control from LTDC_SRCR enabled)

1 (B_0x1): global reload masked for this layer (control from LTDC_SRCR disabled)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32