stm32 /stm32n6 /STM32N645 /MDF1 /MDF_DLY4CR

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Interpret as MDF_DLY4CR

31282724232019161512118743000000000000000000000000000000000000000000 (B_0x0)SKPDLY0 (B_0x0)SKPBF

SKPDLY=B_0x0, SKPBF=B_0x0

Description

MDF delay control register 4

Fields

SKPDLY

Delay to apply to a bitstream

0 (B_0x0): No input sample skipped

1 (B_0x1): 1 input sample skipped

SKPBF

Skip busy flag

0 (B_0x0): MDF ready to accept a new value into SKPDLY[6:0]

1 (B_0x1): Last valid SKPDLY[6:0] still under processing

Links

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