stm32 /stm32n6 /STM32N645 /MDF1 /MDF_GCR

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Interpret as MDF_GCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TRGO 0 (B_0x0)ILVNB

TRGO=B_0x0, ILVNB=B_0x0

Description

MDF global control register

Fields

TRGO

Trigger output control

0 (B_0x0): Write 0 has no effect. Read 0 means that the trigger can be set again to 1.

1 (B_0x1): Write 1 generates a positive pulse on mdf_trgo signal and triggers the acquisition on the enabled filters having ACQMOD[2:0] = 0x1 and selecting TRGO as trigger. Read 1 means that the trigger pulse is still active.

ILVNB

Interleaved number

0 (B_0x0): Interleaved-transfer mode disabled

1 (B_0x1): Data from DFLT0 and DFLT1 are interleaved.

2 (B_0x2): Data from DFLT0, DFLT1 and DFLT2 are interleaved.

15 (B_0xF): Data from DFLT0 to DFLT15 are interleaved.

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