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stm32 /stm32n6 /STM32N645 /MDIOS /MDIOS_CR

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Interpret as MDIOS_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EN 0 (B_0x0)WRIE 0 (B_0x0)RDIE 0 (B_0x0)EIE 0 (B_0x0)DPC 0PORT_ADDRESS

RDIE=B_0x0, EN=B_0x0, DPC=B_0x0, EIE=B_0x0, WRIE=B_0x0

Description

MDIOS configuration register

Fields

EN

peripheral enable

0 (B_0x0): MDIOS is disabled.

1 (B_0x1): MDIOS is enabled and monitoring the MDIO bus (MDC/MDIO).
WRIE

register write interrupt enable

0 (B_0x0): Interrupt is disabled.

1 (B_0x1): Interrupt is enabled.
RDIE

register read interrupt enable

0 (B_0x0): Interrupt is disabled.

1 (B_0x1): Interrupt is enabled.
EIE

error interrupt enable

0 (B_0x0): Interrupt is disabled.

1 (B_0x1): Interrupt is enabled.
DPC

disable preamble check

0 (B_0x0): MDIO master must give preamble before each frame.

1 (B_0x1): MDIO master can send each frame without a preceding preamble, and the MDIOS does not signal a preamble error.
PORT_ADDRESS

slave address

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32