stm32 /stm32n6 /STM32N645 /OTG1 /OTG_DCFG

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Interpret as OTG_DCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DSPD 0 (B_0x0)NZLSOHSK 0DAD0 (B_0x0)PFIVL 0 (B_0x0)ERRATIM 0 (B_0x0)PERSCHIVL

PFIVL=B_0x0, DSPD=B_0x0, ERRATIM=B_0x0, PERSCHIVL=B_0x0, NZLSOHSK=B_0x0

Description

OTG device configuration register

Fields

DSPD

Device speed

0 (B_0x0): High speed

1 (B_0x1): Full speed

NZLSOHSK

Non-zero-length status OUT handshake

0 (B_0x0): Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the device endpoint control register.

1 (B_0x1): Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application.

DAD

Device address

PFIVL

Periodic frame interval

0 (B_0x0): 80% of the frame interval

1 (B_0x1): 85% of the frame interval

2 (B_0x2): 90% of the frame interval

3 (B_0x3): 95% of the frame interval

ERRATIM

Erratic error interrupt mask

0 (B_0x0): Early suspend interrupt is generated on erratic error

1 (B_0x1): Mask early suspend interrupt on erratic error

PERSCHIVL

Periodic schedule interval

0 (B_0x0): 25% of (micro)frame

1 (B_0x1): 50% of (micro)frame

2 (B_0x2): 75% of (micro)frame

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