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stm32 /stm32n6 /STM32N645 /OTG1 /OTG_GUSBCFG

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Interpret as OTG_GUSBCFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TOCAL0TRDT0 (B_0x0)PHYLPC 0 (B_0x0)TSDPS 0 (B_0x0)FHMOD 0 (B_0x0)FDMOD

TSDPS=B_0x0, PHYLPC=B_0x0, FHMOD=B_0x0, FDMOD=B_0x0

Description

OTG USB configuration register

Fields

TOCAL

FS timeout calibration
TRDT

USB turnaround time
PHYLPC

PHY Low-power clock select

0 (B_0x0): 480 MHz internal PLL clock

1 (B_0x1): 48 MHz external clock
TSDPS

TermSel DLine pulsing selection

0 (B_0x0): Data line pulsing using utmi_txvalid (default)

1 (B_0x1): Data line pulsing using utmi_termsel
FHMOD

Force host mode

0 (B_0x0): Normal mode

1 (B_0x1): Force host mode
FDMOD

Force device mode

0 (B_0x0): Normal mode

1 (B_0x1): Force device mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32