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stm32 /stm32n6 /STM32N645 /PWR /PWR_BDCR2

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Interpret as PWR_BDCR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BKPRBSEN

BKPRBSEN=B_0x0

Description

PWR backup domain control register 2

Fields

BKPRBSEN

Backup RAM backup supply enable (used to maintain BKPRAM content in Standby and V less than sub>BAT less than /sub> modes).

0 (B_0x0): BKPSRAM backup supply disabled

1 (B_0x1): BKPSRAM backup supply enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32