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stm32 /stm32n6 /STM32N645 /RCC /RCC_AHB2RSTR

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Interpret as RCC_AHB2RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RAMCFGRST 0 (B_0x0)MDF1RST 0 (B_0x0)ADF1RST

ADF1RST=B_0x0, RAMCFGRST=B_0x0, MDF1RST=B_0x0

Description

RCC AHB2 reset register

Fields

RAMCFGRST

RAMCFG reset

0 (B_0x0): RAMCFG is not under reset (default after reset)

1 (B_0x1): RAMCFG is under reset
MDF1RST

MDF1 reset

0 (B_0x0): MDF1 is not under reset (default after reset)

1 (B_0x1): MDF1 is under reset
ADF1RST

ADF1 reset

0 (B_0x0): ADF1 is not under reset (default after reset)

1 (B_0x1): ADF1 is under reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32