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stm32 /stm32n6 /STM32N645 /RCC /RCC_AHB4LPENR

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Interpret as RCC_AHB4LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPIOALPEN 0 (B_0x0)GPIOBLPEN 0 (B_0x0)GPIOCLPEN 0 (B_0x0)GPIODLPEN 0 (B_0x0)GPIOELPEN 0 (B_0x0)GPIOFLPEN 0 (B_0x0)GPIOGLPEN 0 (B_0x0)GPIOHLPEN 0 (B_0x0)GPIONLPEN 0 (B_0x0)GPIOOLPEN 0 (B_0x0)GPIOPLPEN 0 (B_0x0)GPIOQLPEN 0 (B_0x0)PWRLPEN 0 (B_0x0)CRCLPEN

CRCLPEN=B_0x0, GPIOPLPEN=B_0x0, GPIOELPEN=B_0x0, GPIOOLPEN=B_0x0, GPIOBLPEN=B_0x0, GPIONLPEN=B_0x0, GPIOHLPEN=B_0x0, GPIOFLPEN=B_0x0, GPIOCLPEN=B_0x0, PWRLPEN=B_0x0, GPIOGLPEN=B_0x0, GPIOQLPEN=B_0x0, GPIODLPEN=B_0x0, GPIOALPEN=B_0x0

Description

RCC AHB4 Sleep enable register

Fields

GPIOALPEN

GPIOA sleep enable

0 (B_0x0): GPIOA is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOA is enabled in Sleep mode
GPIOBLPEN

GPIOB sleep enable

0 (B_0x0): GPIOB is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOB is enabled in Sleep mode
GPIOCLPEN

GPIOC sleep enable

0 (B_0x0): GPIOC is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOC is enabled in Sleep mode
GPIODLPEN

GPIOD sleep enable

0 (B_0x0): GPIOD is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOD is enabled in Sleep mode
GPIOELPEN

GPIOE sleep enable

0 (B_0x0): GPIOE is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOE is enabled in Sleep mode
GPIOFLPEN

GPIOF sleep enable

0 (B_0x0): GPIOF is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOF is enabled in Sleep mode
GPIOGLPEN

GPIOG sleep enable

0 (B_0x0): GPIOG is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOG is enabled in Sleep mode
GPIOHLPEN

GPIOH sleep enable

0 (B_0x0): GPIOH is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOH is enabled in Sleep mode
GPIONLPEN

GPION sleep enable

0 (B_0x0): GPION is disabled in Sleep mode (default after reset)

1 (B_0x1): GPION is enabled in Sleep mode
GPIOOLPEN

GPIOO sleep enable

0 (B_0x0): GPIOO is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOO is enabled in Sleep mode
GPIOPLPEN

GPIOP sleep enable

0 (B_0x0): GPIOP is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOP is enabled in Sleep mode
GPIOQLPEN

GPIOQ sleep enable

0 (B_0x0): GPIOQ is disabled in Sleep mode (default after reset)

1 (B_0x1): GPIOQ is enabled in Sleep mode
PWRLPEN

PWR sleep enable

0 (B_0x0): PWR is disabled in Sleep mode

1 (B_0x1): PWR is enabled in Sleep mode (default after reset)
CRCLPEN

CRC sleep enable

0 (B_0x0): CRC is disabled in Sleep mode (default after reset)

1 (B_0x1): CRC is enabled in Sleep mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32