stm32 /stm32n6 /STM32N645 /RCC /RCC_AHB5LPENCR

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Interpret as RCC_AHB5LPENCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HPDMA1LPENC)HPDMA1LPENC 0 (DMA2DLPENC)DMA2DLPENC 0 (JPEGLPENC)JPEGLPENC 0 (FMCLPENC)FMCLPENC 0 (XSPI1LPENC)XSPI1LPENC 0 (PSSILPENC)PSSILPENC 0 (SDMMC2LPENC)SDMMC2LPENC 0 (SDMMC1LPENC)SDMMC1LPENC 0 (XSPI2LPENC)XSPI2LPENC 0 (XSPIMLPENC)XSPIMLPENC 0 (MCE1LPENC)MCE1LPENC 0 (MCE2LPENC)MCE2LPENC 0 (MCE3LPENC)MCE3LPENC 0 (XSPI3LPENC)XSPI3LPENC 0 (MCE4LPENC)MCE4LPENC 0 (GFXMMULPENC)GFXMMULPENC 0 (GPULPENC)GPULPENC 0 (ETH1MACLPENC)ETH1MACLPENC 0 (ETH1TXLPENC)ETH1TXLPENC 0 (ETH1RXLPENC)ETH1RXLPENC 0 (ETH1LPENC)ETH1LPENC 0 (OTG1LPENC)OTG1LPENC 0 (OTGPHY1LPENC)OTGPHY1LPENC 0 (OTGPHY2LPENC)OTGPHY2LPENC 0 (OTG2LPENC)OTG2LPENC 0 (NPUCACHELPENC)NPUCACHELPENC 0 (NPULPENC)NPULPENC

Description

RCC AHB5 Sleep enable register

Fields

HPDMA1LPENC

HPDMA1 sleep enable

DMA2DLPENC

DMA2D sleep enable

JPEGLPENC

JPEG sleep enable

FMCLPENC

FMC sleep enable

XSPI1LPENC

XSPI1 sleep enable

PSSILPENC

PSSI sleep enable

SDMMC2LPENC

SDMMC2 sleep enable

SDMMC1LPENC

SDMMC1 sleep enable

XSPI2LPENC

XSPI2 sleep enable

XSPIMLPENC

XSPIM sleep enable

MCE1LPENC

MCE1 sleep enable

MCE2LPENC

MCE2 sleep enable

MCE3LPENC

MCE3 sleep enable

XSPI3LPENC

XSPI3 sleep enable

MCE4LPENC

MCE4 sleep enable

GFXMMULPENC

GFXMMU sleep enable

GPULPENC

GPU sleep enable

ETH1MACLPENC

ETH1MAC sleep enable

ETH1TXLPENC

ETH1TX sleep enable

ETH1RXLPENC

ETH1RX sleep enable

ETH1LPENC

ETH1 sleep enable

OTG1LPENC

OTG1 sleep enable

OTGPHY1LPENC

OTGPHY1 sleep enable

OTGPHY2LPENC

OTGPHY2 sleep enable

OTG2LPENC

OTG2 sleep enable

NPUCACHELPENC

NPUCACHE sleep enable

NPULPENC

NPU sleep enable

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