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stm32 /stm32n6 /STM32N645 /RCC /RCC_AHB5RSTR

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Interpret as RCC_AHB5RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HPDMA1RST 0 (B_0x0)DMA2DRST 0 (B_0x0)JPEGRST 0 (B_0x0)FMCRST 0 (B_0x0)XSPI1RST 0 (B_0x0)PSSIRST 0 (B_0x0)SDMMC2RST 0 (B_0x0)SDMMC1RST 0 (B_0x0)XSPI2RST 0 (B_0x0)XSPIMRST 0 (B_0x0)XSPI3RST 0 (B_0x0)MCE4RST 0 (B_0x0)GFXMMURST 0 (B_0x0)GPURST 0 (B_0x0)SYSCFGOTGHSPHY1RST 0 (B_0x0)SYSCFGOTGHSPHY2RST 0 (B_0x0)ETH1RST 0 (B_0x0)OTG1RST 0 (B_0x0)OTGPHY1RST 0 (B_0x0)OTGPHY2RST 0 (B_0x0)OTG2RST 0 (B_0x0)NPUCACHERST 0 (B_0x0)NPURST

SDMMC1RST=B_0x0, OTGPHY1RST=B_0x0, ETH1RST=B_0x0, OTG2RST=B_0x0, SYSCFGOTGHSPHY2RST=B_0x0, PSSIRST=B_0x0, OTG1RST=B_0x0, NPUCACHERST=B_0x0, OTGPHY2RST=B_0x0, GPURST=B_0x0, XSPI3RST=B_0x0, XSPI1RST=B_0x0, MCE4RST=B_0x0, GFXMMURST=B_0x0, XSPI2RST=B_0x0, JPEGRST=B_0x0, DMA2DRST=B_0x0, SDMMC2RST=B_0x0, HPDMA1RST=B_0x0, SYSCFGOTGHSPHY1RST=B_0x0, FMCRST=B_0x0, NPURST=B_0x0, XSPIMRST=B_0x0

Description

RCC AHB5 reset register

Fields

HPDMA1RST

HPDMA1 reset

0 (B_0x0): HPDMA1 is not under reset (default after reset)

1 (B_0x1): HPDMA1 is under reset
DMA2DRST

DMA2D reset

0 (B_0x0): DMA2D is not under reset (default after reset)

1 (B_0x1): DMA2D is under reset
JPEGRST

JPEG reset

0 (B_0x0): JPEG is not under reset (default after reset)

1 (B_0x1): JPEG is under reset
FMCRST

FMC reset

0 (B_0x0): FMC is not under reset (default after reset)

1 (B_0x1): FMC is under reset
XSPI1RST

XSPI1 reset

0 (B_0x0): XSPI1 is not under reset (default after reset)

1 (B_0x1): XSPI1 is under reset
PSSIRST

PSSI reset

0 (B_0x0): PSSI is not under reset (default after reset)

1 (B_0x1): PSSI is under reset
SDMMC2RST

SDMMC2 reset

0 (B_0x0): SDMMC2 is not under reset (default after reset)

1 (B_0x1): SDMMC2 is under reset
SDMMC1RST

SDMMC1 reset

0 (B_0x0): SDMMC1 is not under reset (default after reset)

1 (B_0x1): SDMMC1 is under reset
XSPI2RST

XSPI2 reset

0 (B_0x0): XSPI2 is not under reset (default after reset)

1 (B_0x1): XSPI2 is under reset
XSPIMRST

XSPIM reset

0 (B_0x0): XSPIM is not under reset (default after reset)

1 (B_0x1): XSPIM is under reset
XSPI3RST

XSPI3 reset

0 (B_0x0): XSPI3 is not under reset (default after reset)

1 (B_0x1): XSPI3 is under reset
MCE4RST

MCE4 reset

0 (B_0x0): MCE4 is not under reset (default after reset)

1 (B_0x1): MCE4 is under reset
GFXMMURST

GFXMMU reset

0 (B_0x0): GFXMMU is not under reset (default after reset)

1 (B_0x1): GFXMMU is under reset
GPURST

GPU reset

0 (B_0x0): GPU is not under reset (default after reset)

1 (B_0x1): GPU is under reset
SYSCFGOTGHSPHY1RST

SYSCFGOTGHSPHY1 reset

0 (B_0x0): SYSCFGOTGHSPHY1 is not under reset (default after reset)

1 (B_0x1): SYSCFGOTGHSPHY1 is under reset
SYSCFGOTGHSPHY2RST

SYSCFGOTGHSPHY2 reset

0 (B_0x0): SYSCFGOTGHSPHY2 is not under reset (default after reset)

1 (B_0x1): SYSCFGOTGHSPHY2 is under reset
ETH1RST

ETH1 reset

0 (B_0x0): ETH1 is not under reset (default after reset)

1 (B_0x1): ETH1 is under reset
OTG1RST

OTG1 reset

0 (B_0x0): OTG1 is not under reset (default after reset)

1 (B_0x1): OTG1 is under reset
OTGPHY1RST

OTGPHY1 reset

0 (B_0x0): OTGPHY1 is not under reset (default after reset)

1 (B_0x1): OTGPHY1 is under reset
OTGPHY2RST

OTGPHY2 reset

0 (B_0x0): OTGPHY2 is not under reset (default after reset)

1 (B_0x1): OTGPHY2 is under reset
OTG2RST

OTG2 reset

0 (B_0x0): OTG2 is not under reset (default after reset)

1 (B_0x1): OTG2 is under reset
NPUCACHERST

NPUCACHE reset

0 (B_0x0): NPUCACHE is not under reset (default after reset)

1 (B_0x1): NPUCACHE is under reset
NPURST

NPU reset

0 (B_0x0): NPU is not under reset (default after reset)

1 (B_0x1): NPU is under reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32