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stm32 /stm32n6 /STM32N645 /RCC /RCC_APB1HLPENR

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Interpret as RCC_APB1HLPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MDIOSLPEN 0 (B_0x0)FDCANLPEN 0 (B_0x0)UCPD1LPEN

FDCANLPEN=B_0x0, UCPD1LPEN=B_0x0, MDIOSLPEN=B_0x0

Description

RCC APB1H Sleep enable register

Fields

MDIOSLPEN

MDIOS sleep enable

0 (B_0x0): MDIOS is disabled in Sleep mode (default after reset)

1 (B_0x1): MDIOS is enabled in Sleep mode
FDCANLPEN

FDCAN sleep enable

0 (B_0x0): FDCAN is disabled in Sleep mode (default after reset)

1 (B_0x1): FDCAN is enabled in Sleep mode
UCPD1LPEN

UCPD1 sleep enable

0 (B_0x0): UCPD1 is disabled in Sleep mode (default after reset)

1 (B_0x1): UCPD1 is enabled in Sleep mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32