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stm32 /stm32n6 /STM32N645 /RCC /RCC_APB1HRSTR

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Interpret as RCC_APB1HRSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MDIOSRST 0 (B_0x0)FDCANRST 0 (B_0x0)UCPD1RST

UCPD1RST=B_0x0, FDCANRST=B_0x0, MDIOSRST=B_0x0

Description

RCC APB1H reset register

Fields

MDIOSRST

MDIOS reset

0 (B_0x0): MDIOS is not under reset (default after reset)

1 (B_0x1): MDIOS is under reset
FDCANRST

FDCAN reset

0 (B_0x0): FDCAN is not under reset (default after reset)

1 (B_0x1): FDCAN is under reset
UCPD1RST

UCPD1 reset

0 (B_0x0): UCPD1 is not under reset (default after reset)

1 (B_0x1): UCPD1 is under reset

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32