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stm32 /stm32n6 /STM32N645 /RCC /RCC_APB1LLPENR

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Interpret as RCC_APB1LLPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM2LPEN 0 (B_0x0)TIM3LPEN 0 (B_0x0)TIM4LPEN 0 (B_0x0)TIM5LPEN 0 (B_0x0)TIM6LPEN 0 (B_0x0)TIM7LPEN 0 (B_0x0)TIM12LPEN 0 (B_0x0)TIM13LPEN 0 (B_0x0)TIM14LPEN 0 (B_0x0)LPTIM1LPEN 0 (B_0x0)WWDGLPEN 0 (B_0x0)TIM10LPEN 0 (B_0x0)TIM11LPEN 0 (B_0x0)SPI2LPEN 0 (B_0x0)SPI3LPEN 0 (B_0x0)SPDIFRX1LPEN 0 (B_0x0)USART2LPEN 0 (B_0x0)USART3LPEN 0 (B_0x0)UART4LPEN 0 (B_0x0)UART5LPEN 0 (B_0x0)I2C1LPEN 0 (B_0x0)I2C2LPEN 0 (B_0x0)I2C3LPEN 0 (B_0x0)I3C1LPEN 0 (B_0x0)I3C2LPEN 0 (B_0x0)UART7LPEN 0 (B_0x0)UART8LPEN

I2C2LPEN=B_0x0, UART5LPEN=B_0x0, TIM11LPEN=B_0x0, UART7LPEN=B_0x0, UART8LPEN=B_0x0, TIM10LPEN=B_0x0, USART2LPEN=B_0x0, LPTIM1LPEN=B_0x0, I3C1LPEN=B_0x0, SPDIFRX1LPEN=B_0x0, TIM14LPEN=B_0x0, TIM12LPEN=B_0x0, TIM5LPEN=B_0x0, TIM4LPEN=B_0x0, TIM2LPEN=B_0x0, WWDGLPEN=B_0x0, USART3LPEN=B_0x0, I2C3LPEN=B_0x0, SPI2LPEN=B_0x0, TIM13LPEN=B_0x0, TIM3LPEN=B_0x0, TIM6LPEN=B_0x0, I3C2LPEN=B_0x0, I2C1LPEN=B_0x0, UART4LPEN=B_0x0, SPI3LPEN=B_0x0, TIM7LPEN=B_0x0

Description

RCC APB1L Sleep enable register

Fields

TIM2LPEN

TIM2 sleep enable

0 (B_0x0): TIM2 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM2 is enabled in Sleep mode
TIM3LPEN

TIM3 sleep enable

0 (B_0x0): TIM3 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM3 is enabled in Sleep mode
TIM4LPEN

TIM4 sleep enable

0 (B_0x0): TIM4 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM4 is enabled in Sleep mode
TIM5LPEN

TIM5 sleep enable

0 (B_0x0): TIM5 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM5 is enabled in Sleep mode
TIM6LPEN

TIM6 sleep enable

0 (B_0x0): TIM6 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM6 is enabled in Sleep mode
TIM7LPEN

TIM7 sleep enable

0 (B_0x0): TIM7 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM7 is enabled in Sleep mode
TIM12LPEN

TIM12 sleep enable

0 (B_0x0): TIM12 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM12 is enabled in Sleep mode
TIM13LPEN

TIM13 sleep enable

0 (B_0x0): TIM13 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM13 is enabled in Sleep mode
TIM14LPEN

TIM14 sleep enable

0 (B_0x0): TIM14 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM14 is enabled in Sleep mode
LPTIM1LPEN

LPTIM1 sleep enable

0 (B_0x0): LPTIM1 is disabled in Sleep mode (default after reset)

1 (B_0x1): LPTIM1 is enabled in Sleep mode
WWDGLPEN

WWDG sleep enable

0 (B_0x0): WWDG is disabled in Sleep mode (default after reset)

1 (B_0x1): WWDG is enabled in Sleep mode
TIM10LPEN

TIM10 sleep enable

0 (B_0x0): TIM10 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM10 is enabled in Sleep mode
TIM11LPEN

TIM11 sleep enable

0 (B_0x0): TIM11 is disabled in Sleep mode (default after reset)

1 (B_0x1): TIM11 is enabled in Sleep mode
SPI2LPEN

SPI2 sleep enable

0 (B_0x0): SPI2 is disabled in Sleep mode (default after reset)

1 (B_0x1): SPI2 is enabled in Sleep mode
SPI3LPEN

SPI3 sleep enable

0 (B_0x0): SPI3 is disabled in Sleep mode (default after reset)

1 (B_0x1): SPI3 is enabled in Sleep mode
SPDIFRX1LPEN

SPDIFRX1 sleep enable

0 (B_0x0): SPDIFRX1 is disabled in Sleep mode (default after reset)

1 (B_0x1): SPDIFRX1 is enabled in Sleep mode
USART2LPEN

USART2 sleep enable

0 (B_0x0): USART2 is disabled in Sleep mode (default after reset)

1 (B_0x1): USART2 is enabled in Sleep mode
USART3LPEN

USART3 sleep enable

0 (B_0x0): USART3 is disabled in Sleep mode (default after reset)

1 (B_0x1): USART3 is enabled in Sleep mode
UART4LPEN

UART4 sleep enable

0 (B_0x0): UART4 is disabled in Sleep mode (default after reset)

1 (B_0x1): UART4 is enabled in Sleep mode
UART5LPEN

UART5 sleep enable

0 (B_0x0): UART5 is disabled in Sleep mode (default after reset)

1 (B_0x1): UART5 is enabled in Sleep mode
I2C1LPEN

I2C1 sleep enable

0 (B_0x0): I2C1 is disabled in Sleep mode (default after reset)

1 (B_0x1): I2C1 is enabled in Sleep mode
I2C2LPEN

I2C2 sleep enable

0 (B_0x0): I2C2 is disabled in Sleep mode (default after reset)

1 (B_0x1): I2C2 is enabled in Sleep mode
I2C3LPEN

I2C3 sleep enable

0 (B_0x0): I2C3 is disabled in Sleep mode (default after reset)

1 (B_0x1): I2C3 is enabled in Sleep mode
I3C1LPEN

I3C1 sleep enable

0 (B_0x0): I3C1 is disabled in Sleep mode (default after reset)

1 (B_0x1): I3C1 is enabled in Sleep mode
I3C2LPEN

I3C2 sleep enable

0 (B_0x0): I3C2 is disabled in Sleep mode (default after reset)

1 (B_0x1): I3C2 is enabled in Sleep mode
UART7LPEN

UART7 sleep enable

0 (B_0x0): UART7 is disabled in Sleep mode (default after reset)

1 (B_0x1): UART7 is enabled in Sleep mode
UART8LPEN

UART8 sleep enable

0 (B_0x0): UART8 is disabled in Sleep mode (default after reset)

1 (B_0x1): UART8 is enabled in Sleep mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32