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stm32 /stm32n6 /STM32N645 /RCC /RCC_APB2RSTR

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Interpret as RCC_APB2RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM1RST 0 (B_0x0)TIM8RST 0 (B_0x0)USART1RST 0 (B_0x0)USART6RST 0 (B_0x0)UART9RST 0 (B_0x0)USART10RST 0 (B_0x0)SPI1RST 0 (B_0x0)SPI4RST 0 (B_0x0)TIM18RST 0 (B_0x0)TIM15RST 0 (B_0x0)TIM16RST 0 (B_0x0)TIM17RST 0 (B_0x0)TIM9RST 0 (B_0x0)SPI5RST 0 (B_0x0)SAI1RST 0 (B_0x0)SAI2RST

TIM15RST=B_0x0, TIM9RST=B_0x0, SAI2RST=B_0x0, TIM17RST=B_0x0, USART10RST=B_0x0, UART9RST=B_0x0, USART6RST=B_0x0, USART1RST=B_0x0, SPI5RST=B_0x0, TIM8RST=B_0x0, TIM18RST=B_0x0, SPI1RST=B_0x0, TIM16RST=B_0x0, SAI1RST=B_0x0, SPI4RST=B_0x0, TIM1RST=B_0x0

Description

RCC APB2 reset register

Fields

TIM1RST

TIM1 reset

0 (B_0x0): TIM1 is not under reset (default after reset)

1 (B_0x1): TIM1 is under reset
TIM8RST

TIM8 reset

0 (B_0x0): TIM8 is not under reset (default after reset)

1 (B_0x1): TIM8 is under reset
USART1RST

USART1 reset

0 (B_0x0): USART1 is not under reset (default after reset)

1 (B_0x1): USART1 is under reset
USART6RST

USART6 reset

0 (B_0x0): USART6 is not under reset (default after reset)

1 (B_0x1): USART6 is under reset
UART9RST

UART9 reset

0 (B_0x0): UART9 is not under reset (default after reset)

1 (B_0x1): UART9 is under reset
USART10RST

USART10 reset

0 (B_0x0): USART10 is not under reset (default after reset)

1 (B_0x1): USART10 is under reset
SPI1RST

SPI1 reset

0 (B_0x0): SPI1 is not under reset (default after reset)

1 (B_0x1): SPI1 is under reset
SPI4RST

SPI4 reset

0 (B_0x0): SPI4 is not under reset (default after reset)

1 (B_0x1): SPI4 is under reset
TIM18RST

TIM18 reset

0 (B_0x0): TIM18 is not under reset (default after reset)

1 (B_0x1): TIM18 is under reset
TIM15RST

TIM15 reset

0 (B_0x0): TIM15 is not under reset (default after reset)

1 (B_0x1): TIM15 is under reset
TIM16RST

TIM16 reset

0 (B_0x0): TIM16 is not under reset (default after reset)

1 (B_0x1): TIM16 is under reset
TIM17RST

TIM17 reset

0 (B_0x0): TIM17 is not under reset (default after reset)

1 (B_0x1): TIM17 is under reset
TIM9RST

TIM9 reset

0 (B_0x0): TIM9 is not under reset (default after reset)

1 (B_0x1): TIM9 is under reset
SPI5RST

SPI5 reset

0 (B_0x0): SPI5 is not under reset (default after reset)

1 (B_0x1): SPI5 is under reset
SAI1RST

SAI1 reset

0 (B_0x0): SAI1 is not under reset (default after reset)

1 (B_0x1): SAI1 is under reset
SAI2RST

SAI2 reset

0 (B_0x0): SAI2 is not under reset (default after reset)

1 (B_0x1): SAI2 is under reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32