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stm32 /stm32n6 /STM32N645 /RCC /RCC_APB4LLPENR

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Interpret as RCC_APB4LLPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HDPLPEN 0 (B_0x0)LPUART1LPEN 0 (B_0x0)SPI6LPEN 0 (B_0x0)I2C4LPEN 0 (B_0x0)LPTIM2LPEN 0 (B_0x0)LPTIM3LPEN 0 (B_0x0)LPTIM4LPEN 0 (B_0x0)LPTIM5LPEN 0 (B_0x0)VREFBUFLPEN 0 (B_0x0)RTCLPEN 0 (B_0x0)RTCAPBLPEN 0 (B_0x0)R2GRETLPEN 0 (B_0x0)R2GNPULPEN 0 (B_0x0)SERFLPEN

LPTIM2LPEN=B_0x0, HDPLPEN=B_0x0, R2GRETLPEN=B_0x0, I2C4LPEN=B_0x0, LPTIM5LPEN=B_0x0, R2GNPULPEN=B_0x0, RTCLPEN=B_0x0, LPTIM4LPEN=B_0x0, LPTIM3LPEN=B_0x0, SERFLPEN=B_0x0, RTCAPBLPEN=B_0x0, LPUART1LPEN=B_0x0, VREFBUFLPEN=B_0x0, SPI6LPEN=B_0x0

Description

RCC APB4L Sleep enable register

Fields

HDPLPEN

HDP sleep enable

0 (B_0x0): HDP is disabled in Sleep mode (default after reset)

1 (B_0x1): HDP is enabled in Sleep mode
LPUART1LPEN

LPUART1 sleep enable

0 (B_0x0): LPUART1 is disabled in Sleep mode (default after reset)

1 (B_0x1): LPUART1 is enabled in Sleep mode
SPI6LPEN

SPI6 sleep enable

0 (B_0x0): SPI6 is disabled in Sleep mode (default after reset)

1 (B_0x1): SPI6 is enabled in Sleep mode
I2C4LPEN

I2C4 sleep enable

0 (B_0x0): I2C4 is disabled in Sleep mode (default after reset)

1 (B_0x1): I2C4 is enabled in Sleep mode
LPTIM2LPEN

LPTIM2 sleep enable

0 (B_0x0): LPTIM2 is disabled in Sleep mode (default after reset)

1 (B_0x1): LPTIM2 is enabled in Sleep mode
LPTIM3LPEN

LPTIM3 sleep enable

0 (B_0x0): LPTIM3 is disabled in Sleep mode (default after reset)

1 (B_0x1): LPTIM3 is enabled in Sleep mode
LPTIM4LPEN

LPTIM4 sleep enable

0 (B_0x0): LPTIM4 is disabled in Sleep mode (default after reset)

1 (B_0x1): LPTIM4 is enabled in Sleep mode
LPTIM5LPEN

LPTIM5 sleep enable

0 (B_0x0): LPTIM5 is disabled in Sleep mode (default after reset)

1 (B_0x1): LPTIM5 is enabled in Sleep mode
VREFBUFLPEN

VREFBUF sleep enable

0 (B_0x0): VREFBUF is disabled in Sleep mode (default after reset)

1 (B_0x1): VREFBUF is enabled in Sleep mode
RTCLPEN

RTC sleep enable

0 (B_0x0): RTC is disabled in Sleep mode (default after reset)

1 (B_0x1): RTC is enabled in Sleep mode
RTCAPBLPEN

RTCAPB sleep enable

0 (B_0x0): RTCAPB is disabled in Sleep mode (default after reset)

1 (B_0x1): RTCAPB is enabled in Sleep mode
R2GRETLPEN

R2GRET sleep enable

0 (B_0x0): R2GRET is disabled in Sleep mode (default after reset)

1 (B_0x1): R2GRET is enabled in Sleep mode
R2GNPULPEN

R2GNPU sleep enable

0 (B_0x0): R2GNPU is disabled in Sleep mode (default after reset)

1 (B_0x1): R2GNPU is enabled in Sleep mode
SERFLPEN

SERF sleep enable

0 (B_0x0): SERF is disabled in Sleep mode (default after reset)

1 (B_0x1): SERF is enabled in Sleep mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32