stm32 /stm32n6 /STM32N645 /RCC /RCC_APB4LRSTR

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Interpret as RCC_APB4LRSTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HDPRST 0 (B_0x0)LPUART1RST 0 (B_0x0)SPI6RST 0 (B_0x0)I2C4RST 0 (B_0x0)LPTIM2RST 0 (B_0x0)LPTIM3RST 0 (B_0x0)LPTIM4RST 0 (B_0x0)LPTIM5RST 0 (B_0x0)VREFBUFRST 0 (B_0x0)RTCRST 0 (B_0x0)R2GRETRST 0 (B_0x0)R2GNPURST 0 (B_0x0)SERFRST

SERFRST=B_0x0, LPTIM2RST=B_0x0, R2GRETRST=B_0x0, LPTIM5RST=B_0x0, I2C4RST=B_0x0, SPI6RST=B_0x0, R2GNPURST=B_0x0, HDPRST=B_0x0, VREFBUFRST=B_0x0, LPTIM4RST=B_0x0, LPTIM3RST=B_0x0, LPUART1RST=B_0x0, RTCRST=B_0x0

Description

RCC APB4L reset register

Fields

HDPRST

HDP reset

0 (B_0x0): HDP is not under reset (default after reset)

1 (B_0x1): HDP is under reset

LPUART1RST

LPUART1 reset

0 (B_0x0): LPUART1 is not under reset (default after reset)

1 (B_0x1): LPUART1 is under reset

SPI6RST

SPI6 reset

0 (B_0x0): SPI6 is not under reset (default after reset)

1 (B_0x1): SPI6 is under reset

I2C4RST

I2C4 reset

0 (B_0x0): I2C4 is not under reset (default after reset)

1 (B_0x1): I2C4 is under reset

LPTIM2RST

LPTIM2 reset

0 (B_0x0): LPTIM2 is not under reset (default after reset)

1 (B_0x1): LPTIM2 is under reset

LPTIM3RST

LPTIM3 reset

0 (B_0x0): LPTIM3 is not under reset (default after reset)

1 (B_0x1): LPTIM3 is under reset

LPTIM4RST

LPTIM4 reset

0 (B_0x0): LPTIM4 is not under reset (default after reset)

1 (B_0x1): LPTIM4 is under reset

LPTIM5RST

LPTIM5 reset

0 (B_0x0): LPTIM5 is not under reset (default after reset)

1 (B_0x1): LPTIM5 is under reset

VREFBUFRST

VREFBUF reset

0 (B_0x0): VREFBUF is not under reset (default after reset)

1 (B_0x1): VREFBUF is under reset

RTCRST

RTC reset

0 (B_0x0): RTC is not under reset (default after reset)

1 (B_0x1): RTC is under reset

R2GRETRST

R2GRET reset

0 (B_0x0): R2GRET is not under reset (default after reset)

1 (B_0x1): R2GRET is under reset

R2GNPURST

R2GNPU reset

0 (B_0x0): R2GNPU is not under reset (default after reset)

1 (B_0x1): R2GNPU is under reset

SERFRST

SERF reset

0 (B_0x0): SERF is not under reset (default after reset)

1 (B_0x1): SERF is under reset

Links

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