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stm32 /stm32n6 /STM32N645 /RCC /RCC_APB5ENR

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Interpret as RCC_APB5ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LTDCEN 0 (B_0x0)DCMIPPEN 0 (B_0x0)GFXTIMEN 0 (B_0x0)VENCEN 0 (B_0x0)CSIEN

GFXTIMEN=B_0x0, LTDCEN=B_0x0, VENCEN=B_0x0, DCMIPPEN=B_0x0, CSIEN=B_0x0

Description

RCC APB5 enable register

Fields

LTDCEN

LTDC enable

0 (B_0x0): LTDC is disabled (default after reset)

1 (B_0x1): LTDC is enabled
DCMIPPEN

DCMIPP enable

0 (B_0x0): DCMIPP is disabled (default after reset)

1 (B_0x1): DCMIPP is enabled
GFXTIMEN

GFXTIM enable

0 (B_0x0): GFXTIM is disabled (default after reset)

1 (B_0x1): GFXTIM is enabled
VENCEN

VENC enable

0 (B_0x0): VENC is disabled (default after reset)

1 (B_0x1): VENC is enabled
CSIEN

CSI enable

0 (B_0x0): CSI is disabled (default after reset)

1 (B_0x1): CSI is enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32