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stm32 /stm32n6 /STM32N645 /RCC /RCC_APB5LPENR

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Interpret as RCC_APB5LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LTDCLPEN 0 (B_0x0)DCMIPPLPEN 0 (B_0x0)GFXTIMLPEN 0 (B_0x0)VENCLPEN 0 (B_0x0)CSILPEN

DCMIPPLPEN=B_0x0, LTDCLPEN=B_0x0, CSILPEN=B_0x0, VENCLPEN=B_0x0, GFXTIMLPEN=B_0x0

Description

RCC APB5 Sleep enable register

Fields

LTDCLPEN

LTDC sleep enable

0 (B_0x0): LTDC is disabled in Sleep mode (default after reset)

1 (B_0x1): LTDC is enabled in Sleep mode
DCMIPPLPEN

DCMIPP sleep enable

0 (B_0x0): DCMIPP is disabled in Sleep mode (default after reset)

1 (B_0x1): DCMIPP is enabled in Sleep mode
GFXTIMLPEN

GFXTIM sleep enable

0 (B_0x0): GFXTIM is disabled in Sleep mode (default after reset)

1 (B_0x1): GFXTIM is enabled in Sleep mode
VENCLPEN

VENC sleep enable

0 (B_0x0): VENC is disabled in Sleep mode (default after reset)

1 (B_0x1): VENC is enabled in Sleep mode
CSILPEN

CSI sleep enable

0 (B_0x0): CSI is disabled in Sleep mode (default after reset)

1 (B_0x1): CSI is enabled in Sleep mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32