RegViz: Visualize RCC

stm32 /stm32n6 /STM32N645 /RCC /RCC_CIFR

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Interpret as RCC_CIFR

HSERDYF=B_0x0, PLL4RDYF=B_0x0, PLL1RDYF=B_0x0, PLL2RDYF=B_0x0, WKUPF=B_0x0, HSIRDYF=B_0x0, HSECSSF=B_0x0, LSERDYF=B_0x0, PLL3RDYF=B_0x0, LSIRDYF=B_0x0, MSIRDYF=B_0x0, LSECSSF=B_0x0

Description

RCC clock-source interrupt flag register

Fields

LSIRDYF	LSI ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the LSI (default after reset) 1 (B_0x1): clock ready interrupt caused by the LSI
LSERDYF	LSE ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the LSE (default after reset) 1 (B_0x1): clock ready interrupt caused by the LSE
MSIRDYF	MSI ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the MSI (default after reset) 1 (B_0x1): clock ready interrupt caused by the MSI
HSIRDYF	HSI ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the HSI (default after reset) 1 (B_0x1): clock ready interrupt caused by the HSI
HSERDYF	HSE ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the HSE (default after reset) 1 (B_0x1): clock ready interrupt caused by the HSE
PLL1RDYF	PLL1 ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the PLL1 (default after reset) 1 (B_0x1): clock ready interrupt caused by the PLL1
PLL2RDYF	PLL2 ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the PLL2 (default after reset) 1 (B_0x1): clock ready interrupt caused by the PLL2
PLL3RDYF	PLL3 ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the PLL3 (default after reset) 1 (B_0x1): clock ready interrupt caused by the PLL3
PLL4RDYF	PLL4 ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the PLL4 (default after reset) 1 (B_0x1): clock ready interrupt caused by the PLL4
LSECSSF	LSE ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the LSE (default after reset) 1 (B_0x1): clock ready interrupt caused by the LSE
HSECSSF	HSE ready interrupt flag 0 (B_0x0): no clock ready interrupt caused by the HSE (default after reset) 1 (B_0x1): clock ready interrupt caused by the HSE
WKUPF	CPU wakeup from Stop interrupt flag 0 (B_0x0): no wakeup interrupt caused by the PWR (default after reset) 1 (B_0x1): wakeup interrupt caused by the PWR

Links

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