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stm32 /stm32n6 /STM32N645 /RCC /RCC_DIVLPENR

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Interpret as RCC_DIVLPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IC1LPEN 0 (B_0x0)IC2LPEN 0 (B_0x0)IC3LPEN 0 (B_0x0)IC4LPEN 0 (B_0x0)IC5LPEN 0 (B_0x0)IC6LPEN 0 (B_0x0)IC7LPEN 0 (B_0x0)IC8LPEN 0 (B_0x0)IC9LPEN 0 (B_0x0)IC10LPEN 0 (B_0x0)IC11LPEN 0 (B_0x0)IC12LPEN 0 (B_0x0)IC13LPEN 0 (B_0x0)IC14LPEN 0 (B_0x0)IC15LPEN 0 (B_0x0)IC16LPEN 0 (B_0x0)IC17LPEN 0 (B_0x0)IC18LPEN 0 (B_0x0)IC19LPEN 0 (B_0x0)IC20LPEN

IC13LPEN=B_0x0, IC18LPEN=B_0x0, IC3LPEN=B_0x0, IC8LPEN=B_0x0, IC1LPEN=B_0x0, IC12LPEN=B_0x0, IC6LPEN=B_0x0, IC7LPEN=B_0x0, IC15LPEN=B_0x0, IC17LPEN=B_0x0, IC11LPEN=B_0x0, IC14LPEN=B_0x0, IC20LPEN=B_0x0, IC19LPEN=B_0x0, IC16LPEN=B_0x0, IC10LPEN=B_0x0, IC9LPEN=B_0x0, IC5LPEN=B_0x0, IC4LPEN=B_0x0, IC2LPEN=B_0x0

Description

RCC dividers Sleep enable register

Fields

IC1LPEN

IC1 sleep enable

0 (B_0x0): IC1 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC1 is enabled in Sleep mode
IC2LPEN

IC2 sleep enable

0 (B_0x0): IC2 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC2 is enabled in Sleep mode
IC3LPEN

IC3 sleep enable

0 (B_0x0): IC3 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC3 is enabled in Sleep mode
IC4LPEN

IC4 sleep enable

0 (B_0x0): IC4 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC4 is enabled in Sleep mode
IC5LPEN

IC5 sleep enable

0 (B_0x0): IC5 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC5 is enabled in Sleep mode
IC6LPEN

IC6 sleep enable

0 (B_0x0): IC6 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC6 is enabled in Sleep mode
IC7LPEN

IC7 sleep enable

0 (B_0x0): IC7 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC7 is enabled in Sleep mode
IC8LPEN

IC8 sleep enable

0 (B_0x0): IC8 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC8 is enabled in Sleep mode
IC9LPEN

IC9 sleep enable

0 (B_0x0): IC9 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC9 is enabled in Sleep mode
IC10LPEN

IC10 sleep enable

0 (B_0x0): IC10 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC10 is enabled in Sleep mode
IC11LPEN

IC11 sleep enable

0 (B_0x0): IC11 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC11 is enabled in Sleep mode
IC12LPEN

IC12 sleep enable

0 (B_0x0): IC12 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC12 is enabled in Sleep mode
IC13LPEN

IC13 sleep enable

0 (B_0x0): IC13 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC13 is enabled in Sleep mode
IC14LPEN

IC14 sleep enable

0 (B_0x0): IC14 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC14 is enabled in Sleep mode
IC15LPEN

IC15 sleep enable

0 (B_0x0): IC15 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC15 is enabled in Sleep mode
IC16LPEN

IC16 sleep enable

0 (B_0x0): IC16 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC16 is enabled in Sleep mode
IC17LPEN

IC17 sleep enable

0 (B_0x0): IC17 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC17 is enabled in Sleep mode
IC18LPEN

IC18 sleep enable

0 (B_0x0): IC18 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC18 is enabled in Sleep mode
IC19LPEN

IC19 sleep enable

0 (B_0x0): IC19 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC19 is enabled in Sleep mode
IC20LPEN

IC20 sleep enable

0 (B_0x0): IC20 is disabled in Sleep mode (default after reset)

1 (B_0x1): IC20 is enabled in Sleep mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32