stm32 /stm32n6 /STM32N645 /RCC /RCC_HSIMCR

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Interpret as RCC_HSIMCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0HSIREF0HSIDEV0 (B_0x0)HSIMONEN

HSIMONEN=B_0x0

Description

RCC HSI monitor control register

Fields

HSIREF

HSI clock cycle counter reference value.

HSIDEV

HSI clock count deviation value

HSIMONEN

HSI clock period monitor enable

0 (B_0x0): Writing ‘0’ disables the HSI clock period monitoring, reading ‘0’ means that the HSI clock period monitoring is disabled

1 (B_0x1): Writing ‘1’ enables the HSI clock period monitoring, reading ‘1’ means that the HSI clock period monitoring is enabled

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