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stm32 /stm32n6 /STM32N645 /RCC /RCC_IC18CFGR

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Interpret as RCC_IC18CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IC18INT0 (B_0x0)IC18SEL

IC18INT=B_0x0, IC18SEL=B_0x0

Description

RCC IC18 configuration register

Fields

IC18INT

Divider IC18 integer division factor

0 (B_0x0): IC18 = pllx_ck (default after reset)

1 (B_0x1): IC18 = pllx_ck / 2

2 (B_0x2): IC18 = pllx_ck / 3

3 (B_0x3): IC18 = pllx_ck / 4

255 (B_0xFF): IC18 = pllx_ck / 256
IC18SEL

Divider IC18 Source Selection

0 (B_0x0): pll1_ck is selected

1 (B_0x1): pll2_ck is selected

2 (B_0x2): hsi_ck = hsi_osc_ck / 4

3 (B_0x3): hsi_ck = hsi_osc_ck / 8

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32