Regviz

stm32 /stm32n6 /STM32N645 /RCC /RCC_IC20CFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCC_IC20CFGR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/RCC/RCC_IC20CFGR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IC20INT0 (B_0x0)IC20SEL

IC20SEL=B_0x0, IC20INT=B_0x0

Description

RCC IC20 configuration register

Fields

IC20INT

Divider IC20 integer division factor

0 (B_0x0): IC20 = pllx_ck (default after reset)

1 (B_0x1): IC20 = pllx_ck / 2

2 (B_0x2): IC20 = pllx_ck / 3

3 (B_0x3): IC20 = pllx_ck / 4

255 (B_0xFF): IC20 = pllx_ck / 256
IC20SEL

Divider IC20 Source Selection

0 (B_0x0): pll1_ck is selected

1 (B_0x1): pll2_ck is selected

2 (B_0x2): hsi_ck = hsi_osc_ck / 4

3 (B_0x3): hsi_ck = hsi_osc_ck / 8

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32