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stm32 /stm32n6 /STM32N645 /RCC /RCC_LOCKCFGR1

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Interpret as RCC_LOCKCFGR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PLL1LOCK 0 (B_0x0)PLL2LOCK 0 (B_0x0)PLL3LOCK 0 (B_0x0)PLL4LOCK

PLL4LOCK=B_0x0, PLL1LOCK=B_0x0, PLL2LOCK=B_0x0, PLL3LOCK=B_0x0

Description

RCC PLL lock configuration register1

Fields

PLL1LOCK

Defines the lock protection of the PLL1 PLL configuration bits.

0 (B_0x0): PLL1 configuration bits are accessible by non-lock software only (default after reset)

1 (B_0x1): PLL1 configuration bits are accessible by lock software only
PLL2LOCK

Defines the lock protection of the PLL2 PLL configuration bits.

0 (B_0x0): PLL2 configuration bits are accessible by non-lock software only (default after reset)

1 (B_0x1): PLL2 configuration bits are accessible by lock software only
PLL3LOCK

Defines the lock protection of the PLL3 PLL configuration bits.

0 (B_0x0): PLL3 configuration bits are accessible by non-lock software only (default after reset)

1 (B_0x1): PLL3 configuration bits are accessible by lock software only
PLL4LOCK

Defines the lock protection of the PLL4 PLL configuration bits.

0 (B_0x0): PLL4 configuration bits are accessible by non-lock software only (default after reset)

1 (B_0x1): PLL4 configuration bits are accessible by lock software only

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32