PLL1DIVM=B_0x0, PLL1BYP=B_0x0, PLL1SEL=B_0x0
RCC PLL1 configuration register 1
| PLL1DIVN | PLL1 Integer part for the VCO multiplication factor |
| PLL1DIVM | PLL1 reference input clock divide frequency ratio 0 (B_0x0): Not applicable when PLL is enabled 1 (B_0x1): reference clock is divided by 1 (min value) 2 (B_0x2): reference clock is divided by 2 63 (B_0x3F): reference clock is divided by 63 |
| PLL1BYP | PLL1 bypass 0 (B_0x0): PLL output is driven by the VCO, via the optional POSTDIV division 1 (B_0x1): PLL output is bypassed and driven by the PLL reference clock (default after reset) |
| PLL1SEL | PLL1 source selection of the reference clock 0 (B_0x0): hsi_ck selected as reference clock 1 (B_0x1): msi_ck selected as reference clock 2 (B_0x2): hse_ck selected as reference clock 3 (B_0x3): I2S_CKIN selected as reference clock |