PLL1PDIV2=B_0x0, PLL1MODSPRDW=B_0x0, PLL1PDIVEN=B_0x0, PLL1MODDSEN=B_0x0, PLL1PDIV1=B_0x0, PLL1MODSSDIS=B_0x0, PLL1DACEN=B_0x0, PLL1MODSSRST=B_0x0
RCC PLL1 configuration register 3
| PLL1MODSSRST | PLL1 Modulation Spread Spectrum reset 0 (B_0x0): The PLL1 modulation Spread Spectrum reset module is released 1 (B_0x1): The PLL1 modulation Spread Spectrum reset module is asserted (default after reset) |
| PLL1DACEN | PLL1 noise canceling DAC enable in fractional mode. 0 (B_0x0): DAC is not active (default after reset) 1 (B_0x1): DAC is active |
| PLL1MODSSDIS | PLL1 Modulation Spread-Spectrum Disable 0 (B_0x0): Modulation Spread-Spectrum is active (and Fractional Divide inactive) 1 (B_0x1): Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset) |
| PLL1MODDSEN | PLL1 Modulation Spread-Spectrum (and Fractional Divide) enable 0 (B_0x0): Modulation Spread-Spectrum and Fractional Divide are not active 1 (B_0x1): Modulation Spread-Spectrum and Fractional Divide are active (default after reset) |
| PLL1MODSPRDW | PLL1 Modulation Spread-Spectrum Down 0 (B_0x0): Center-spread modulation selected (default after reset) 1 (B_0x1): Down-spread modulation selected |
| PLL1MODDIV | PLL1 Modulation Division frequency adjustment |
| PLL1MODSPR | PLL1 Modulation Spread depth adjustment |
| PLL1PDIV2 | PLL1 VCO frequency divider level 2 0 (B_0x0): Not applicable 1 (B_0x1): VCO output is divided by 1 (minimum value) (default after reset) 7 (B_0x7): VCO output is divided by 7 |
| PLL1PDIV1 | PLL1 VCO frequency divider level 1 0 (B_0x0): Not applicable 1 (B_0x1): VCO output is divided by 1 (minimum value) (default after reset) 7 (B_0x7): VCO output is divided by 7 |
| PLL1PDIVEN | PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable 0 (B_0x0): POSTDIV1 and POSTDIV2 are powered down 1 (B_0x1): POSTDIV1 and POSTDIV2 dividers are active (default after reset) |