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stm32 /stm32n6 /STM32N645 /RCC /RCC_PUBCFGSR1

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Interpret as RCC_PUBCFGSR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PLL1PUBS)PLL1PUBS 0 (PLL2PUBS)PLL2PUBS 0 (PLL3PUBS)PLL3PUBS 0 (PLL4PUBS)PLL4PUBS

Description

RCC PLL public configuration register1

Fields

PLL1PUBS

Defines the public protection of the PLL1 configuration bits (enable, ready, divider).
PLL2PUBS

Defines the public protection of the PLL2 configuration bits (enable, ready, divider).
PLL3PUBS

Defines the public protection of the PLL3 configuration bits (enable, ready, divider).
PLL4PUBS

Defines the public protection of the PLL4 configuration bits (enable, ready, divider).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32