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stm32 /stm32n6 /STM32N645 /RIFSC /RIFSC_RIMC_CR

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Interpret as RIFSC_RIMC_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GLOCK 0DAPCID

GLOCK=B_0x0

Description

RIFSC RIMC master configuration register

Fields

GLOCK

global lock

0 (B_0x0): RIFSC RIMC registers are writable.

1 (B_0x1): All writes to RIFSC RIMC registers are ignored.
DAPCID

debug access port compartment ID

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32