CPL=B_0x0, FFLUSH=B_0x0, COMP=B_0x0, MUTE=B_0x0, MUTEVAL=B_0x0, FTH=B_0x0, TRIS=B_0x0
SAI configuration register 2
| FTH | FIFO threshold. 0 (B_0x0): FIFO empty 1 (B_0x1): FIFO 2 (B_0x2): FIFO 3 (B_0x3): FIFO 4 (B_0x4): FIFO full |
| FFLUSH | FIFO flush. 0 (B_0x0): No FIFO flush. 1 (B_0x1): FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. In this case data still present in the FIFO are lost (no more transmission or received data lost). Before flushing, SAI DMA stream/interrupt must be disabled |
| TRIS | Tristate management on data line. 0 (B_0x0): SD output line is still driven by the SAI when a slot is inactive. 1 (B_0x1): SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive. |
| MUTE | Mute. 0 (B_0x0): No mute mode. 1 (B_0x1): Mute mode enabled. |
| MUTEVAL | Mute value. 0 (B_0x0): Bit value 0 is sent during the mute mode. 1 (B_0x1): Last values are sent during the mute mode. |
| MUTECNT | Mute counter. |
| CPL | Complement bit. 0 (B_0x0): 1’s complement representation. 1 (B_0x1): 2’s complement representation. |
| COMP | Companding mode. 0 (B_0x0): No companding algorithm 2 (B_0x2): -Law algorithm 3 (B_0x3): A-Law algorithm |