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stm32 /stm32n6 /STM32N645 /SYSCFG /SYSCFG_CM55RWMCR

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Interpret as SYSCFG_CM55RWMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RME_TCM 0RM_TCM0 (BC1_TCM)BC1_TCM 0 (BC2_TCM)BC2_TCM 0 (B_0x0)RME_CACHE 0RM_CACHE 0 (BC1_CACHE)BC1_CACHE 0 (BC2_CACHE)BC2_CACHE

RME_CACHE=B_0x0, RME_TCM=B_0x0

Description

SYSCFG Cortex-CM55 memory RW margin register

Fields

RME_TCM

RW margin enable input for TCM memories

0 (B_0x0): Default RW margin settings

1 (B_0x1): Use external pin RW margin setting
RM_TCM

External RW margin inputs for TCM memories
BC1_TCM

Biasing level adjust input recommended for Vnom
BC2_TCM

Biasing level adjust input recommended for Vnom + 10%
RME_CACHE

RW margin enable input for caches memories

0 (B_0x0): Default RW margin settings

1 (B_0x1): Use external pin RW margin setting
RM_CACHE

External read/write (RW) margin inputs for caches memories
BC1_CACHE

Biasing level adjust input recommended for Vnom.
BC2_CACHE

Biasing level adjust input recommended for Vnom + 10%

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32