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stm32 /stm32n6 /STM32N645 /SYSCFG /SYSCFG_IOCR

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Interpret as SYSCFG_IOCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IOCR

IOCR=B_0x0

Description

SYSCFG /O control register

Fields

IOCR

Digital or analog pins

0 (B_0x0): High-speed mode disabled, or use ADC ANA pin

1 (B_0x1): High-speed mode enabled, or connect internal ADC ANA signal to GPIO

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32