Regviz

stm32 /stm32n6 /STM32N645 /SYSCFG /SYSCFG_VDDIO2CCCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SYSCFG_VDDIO2CCCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/SYSCFG/SYSCFG_VDDIO2CCCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RANSRC0RAPSRC0 (B_0x0)EN 0 (B_0x0)CS

CS=B_0x0, EN=B_0x0

Description

SYSCFG VDDIO2 compensation cell control register

Fields

RANSRC

These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1.
RAPSRC

These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1.
EN

Enables the compensation cell of I/Os supplied by VDDIOx.

0 (B_0x0): VDDIOx I/O compensation cell disabled

1 (B_0x1): VDDIOx I/O compensation cell enabled
CS

Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx.

0 (B_0x0): VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)

1 (B_0x1): VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32