stm32 /stm32n6 /STM32N645 /TIM1 /TIM1_CR2

Capture/compare preloaded control

0 (B_0x0): CCxE, CCxNE and OCxM bits are not preloaded

1 (B_0x1): CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on tim_trgi, depending on the CCUS bit).

Capture/compare control update selection

0 (B_0x0): When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only

1 (B_0x1): When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on tim_trgi

Capture/compare DMA selection

0 (B_0x0): CCx DMA request sent when CCx event occurs

1 (B_0x1): CCx DMA requests sent when update event occurs

MMS[2:0]: Master mode selection

0 (B_0x0): Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on tim_trgo is delayed compared to the actual reset.

1 (B_0x1): Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).

2 (B_0x2): Update - The update event is selected as trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer.

3 (B_0x3): Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (tim_trgo).

4 (B_0x4): Compare - tim_oc1refc signal is used as trigger output (tim_trgo)

5 (B_0x5): Compare - tim_oc2refc signal is used as trigger output (tim_trgo)

6 (B_0x6): Compare - tim_oc3refc signal is used as trigger output (tim_trgo)

7 (B_0x7): Compare - tim_oc4refc signal is used as trigger output (tim_trgo)

tim_ti1 selection

0 (B_0x0): The tim_ti1_in[15:0] multiplexer output is connected to tim_ti1 input

1 (B_0x1): tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input

Output idle state 1 (tim_oc1 output)

0 (B_0x0): tim_oc1=0 (after a dead-time) when MOE=0

1 (B_0x1): tim_oc1=1 (after a dead-time) when MOE=0

Output idle state 1 (tim_oc1n output)

0 (B_0x0): tim_oc1n=0 after a dead-time when MOE=0

1 (B_0x1): tim_oc1n=1 after a dead-time when MOE=0

Output idle state 2 (tim_oc2 output)

Output idle state 2 (tim_oc2n output)

Output idle state 3 (tim_oc3n output)

Output idle state 3 (tim_oc3n output)

Output idle state 4 (tim_oc4 output)

Output idle state 4 (tim_oc4n output)

Output idle state 5 (tim_oc5 output)

Output idle state 6 (tim_oc6 output)

Master mode selection 2

0 (B_0x0): Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on tim_trgo2 is delayed compared to the actual reset.

1 (B_0x1): Enable - the Counter Enable signal CNT_EN is used as trigger output (tim_trgo2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on tim_trgo2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register).

2 (B_0x2): Update - the update event is selected as trigger output (tim_trgo2). For instance, a master timer can then be used as a prescaler for a slave timer.

3 (B_0x3): Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (tim_trgo2).

4 (B_0x4): Compare - tim_oc1refc signal is used as trigger output (tim_trgo2)

5 (B_0x5): Compare - tim_oc2refc signal is used as trigger output (tim_trgo2)

6 (B_0x6): Compare - tim_oc3refc signal is used as trigger output (tim_trgo2)

7 (B_0x7): Compare - tim_oc4refc signal is used as trigger output (tim_trgo2)

8 (B_0x8): Compare - tim_oc5refc signal is used as trigger output (tim_trgo2)

9 (B_0x9): Compare - tim_oc6refc signal is used as trigger output (tim_trgo2)

10 (B_0xA): Compare Pulse - tim_oc4refc rising or falling edges generate pulses on tim_trgo2

11 (B_0xB): Compare pulse - tim_oc6refc rising or falling edges generate pulses on tim_trgo2

12 (B_0xC): Compare pulse - tim_oc4refc or tim_oc6refc rising edges generate pulses on tim_trgo2

13 (B_0xD): Compare pulse - tim_oc4refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2

14 (B_0xE): Compare pulse - tim_oc5refc or tim_oc6refc rising edges generate pulses on tim_trgo2

15 (B_0xF): Compare pulse - tim_oc5refc rising or tim_oc6refc falling edges generate pulses on tim_trgo2

MMS[3]

ADC synchronization

0 (B_0x0): The timer operates independently from the ADC

1 (B_0x1): The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 46.3.32 for requirements.