CEN=B_0x0, UIFREMAP=B_0x0, DITHEN=B_0x0, UDIS=B_0x0, ARPE=B_0x0, URS=B_0x0, CKD=B_0x0, OPM=B_0x0
TIM15 control register 1
| CEN | Counter enable 0 (B_0x0): Counter disabled 1 (B_0x1): Counter enabled |
| UDIS | Update disable 0 (B_0x0): UEV enabled. The Update (UEV) event is generated by one of the following events: 1 (B_0x1): UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. |
| URS | Update request source 0 (B_0x0): Any of the following events generate an update interrupt if enabled. These events can be: 1 (B_0x1): Only counter overflow/underflow generates an update interrupt if enabled |
| OPM | One-pulse mode 0 (B_0x0): Counter is not stopped at update event 1 (B_0x1): Counter stops counting at the next update event (clearing the bit CEN) |
| ARPE | Auto-reload preload enable 0 (B_0x0): TIM15_ARR register is not buffered 1 (B_0x1): TIM15_ARR register is buffered |
| CKD | Clock division 0 (B_0x0): t less than sub>DTS less than /sub>= t less than sub>tim_ker_ck less than /sub> 1 (B_0x1): t less than sub>DTS less than /sub> = 2*t less than sub>tim_ker_ck less than /sub> 2 (B_0x2): t less than sub>DTS less than /sub> = 4*t less than sub>tim_ker_ck less than /sub> |
| UIFREMAP | UIF status bit remapping 0 (B_0x0): No remapping. UIF status bit is not copied to TIM15_CNT register bit 31. 1 (B_0x1): Remapping enabled. UIF status bit is copied to TIM15_CNT register bit 31. |
| DITHEN | Dithering enable 0 (B_0x0): Dithering disabled 1 (B_0x1): Dithering enabled |