LBDL=B_0x0, RXINV=B_0x0, SLVEN=B_0x0, ADDM7=B_0x0, DIS_NSS=B_0x0, LINEN=B_0x0, STOP=B_0x0, RTOEN=B_0x0, CLKEN=B_0x0, CPOL=B_0x0, ABRMOD=B_0x0, TXINV=B_0x0, ABREN=B_0x0, SWAP=B_0x0, DATAINV=B_0x0, MSBFIRST=B_0x0, CPHA=B_0x0, LBCL=B_0x0, LBDIE=B_0x0
USART control register 2
| SLVEN | Synchronous Slave mode enable 0 (B_0x0): Slave mode disabled. 1 (B_0x1): Slave mode enabled. |
| DIS_NSS | When the DIS_NSS bit is set, the NSS pin input is ignored. 0 (B_0x0): SPI slave selection depends on NSS input pin. 1 (B_0x1): SPI slave is always selected and NSS input pin is ignored. |
| ADDM7 | 7-bit Address Detection/4-bit Address Detection 0 (B_0x0): 4-bit address detection 1 (B_0x1): 7-bit address detection (in 8-bit data mode) |
| LBDL | LIN break detection length 0 (B_0x0): 10-bit break detection 1 (B_0x1): 11-bit break detection |
| LBDIE | LIN break detection interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An interrupt is generated whenever LBDF=1 in the USART_ISR register |
| LBCL | Last bit clock pulse 0 (B_0x0): The clock pulse of the last data bit is not output to the CK pin 1 (B_0x1): The clock pulse of the last data bit is output to the CK pin |
| CPHA | Clock phase 0 (B_0x0): The first clock transition is the first data capture edge 1 (B_0x1): The second clock transition is the first data capture edge |
| CPOL | Clock polarity 0 (B_0x0): Steady low value on CK pin outside transmission window 1 (B_0x1): Steady high value on CK pin outside transmission window |
| CLKEN | Clock enable 0 (B_0x0): CK pin disabled 1 (B_0x1): CK pin enabled |
| STOP | stop bits 0 (B_0x0): 1 stop bit 1 (B_0x1): 0.5 stop bit. 2 (B_0x2): 2 stop bits 3 (B_0x3): 1.5 stop bits |
| LINEN | LIN mode enable 0 (B_0x0): LIN mode disabled 1 (B_0x1): LIN mode enabled |
| SWAP | Swap TX/RX pins 0 (B_0x0): TX/RX pins are used as defined in standard pinout 1 (B_0x1): The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. |
| RXINV | RX pin active level inversion 0 (B_0x0): RX pin signal works using the standard logic levels (V less than sub>DD less than /sub> =1/idle, Gnd=0/mark) 1 (B_0x1): RX pin signal values are inverted. ((V less than sub>DD less than /sub> =0/mark, Gnd=1/idle). |
| TXINV | TX pin active level inversion 0 (B_0x0): TX pin signal works using the standard logic levels (V less than sub>DD less than /sub> =1/idle, Gnd=0/mark) 1 (B_0x1): TX pin signal values are inverted. ((V less than sub>DD less than /sub> =0/mark, Gnd=1/idle). |
| DATAINV | Binary data inversion 0 (B_0x0): Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1 (B_0x1): Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. |
| MSBFIRST | Most significant bit first 0 (B_0x0): data is transmitted/received with data bit 0 first, following the start bit. 1 (B_0x1): data is transmitted/received with the MSB (bit 7/8) first, following the start bit. |
| ABREN | Auto baud rate enable 0 (B_0x0): Auto baud rate detection is disabled. 1 (B_0x1): Auto baud rate detection is enabled. |
| ABRMOD | Auto baud rate mode 0 (B_0x0): Measurement of the start bit is used to detect the baud rate. 1 (B_0x1): Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx) 2 (B_0x2): 0x7F frame detection. 3 (B_0x3): 0x55 frame detection |
| RTOEN | Receiver timeout enable 0 (B_0x0): Receiver timeout feature disabled. 1 (B_0x1): Receiver timeout feature enabled. |
| ADD | Address of the USART node |