stm32 /stm32n6 /STM32N645 /WWDG /WWDG_CFR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as WWDG_CFR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0W0 (EWI)EWI 0 (B_0x0)WDGTB

WDGTB=B_0x0

Description

WWDG configuration register

Fields

W

7-bit window value

EWI

Early wakeup interrupt

WDGTB

Timer base

0 (B_0x0): CK counter clock (PCLK div 4096) div 1

1 (B_0x1): CK counter clock (PCLK div 4096) div 2

2 (B_0x2): CK counter clock (PCLK div 4096) div 4

3 (B_0x3): CK counter clock (PCLK div 4096) div 8

4 (B_0x4): CK counter clock (PCLK div 4096) div 16

5 (B_0x5): CK counter clock (PCLK div 4096) div 32

6 (B_0x6): CK counter clock (PCLK div 4096) div 64

7 (B_0x7): CK counter clock (PCLK div 4096) div 128

Links

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