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stm32 /stm32n6 /STM32N645 /XSPI1 /XSPI_TCR

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Interpret as XSPI_TCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DCYC0 (B_0x0)DHQC 0 (B_0x0)SSHIFT

DHQC=B_0x0, SSHIFT=B_0x0

Description

XSPI timing configuration register

Fields

DCYC

Number of dummy cycles
DHQC

Delay hold quarter cycle

0 (B_0x0): no delay hold

1 (B_0x1): 1/4 cycle hold
SSHIFT

Sample shift

0 (B_0x0): no shift

1 (B_0x1): 1/2 cycle shift

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32