stm32 /stm32n6 /STM32N645 /XSPIM /XSPIM_CR

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Interpret as XSPIM_CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MUXEN 0 (B_0x0)MODE 0 (B_0x0)CSSEL_OVR_EN 0 (B_0x0)CSSEL_OVR_O1 0 (B_0x0)CSSEL_OVR_O2 0REQ2ACK_TIME

MODE=B_0x0, MUXEN=B_0x0, CSSEL_OVR_O2=B_0x0, CSSEL_OVR_O1=B_0x0, CSSEL_OVR_EN=B_0x0

Description

XSPIM control register

Fields

MUXEN

Multiplexed mode enable

0 (B_0x0): No multiplexing, hence no arbitration

1 (B_0x1): XSPI1 and XSPI2 are multiplexed over the same bus.

MODE

XSPI multiplexing mode

0 (B_0x0): if MUXEN = 0 direct mode, if MUXEN = 1 arbitration mode to output Port 1

1 (B_0x1): if MUXEN = 0 swapped mode, if MUXEN = 1 arbitration mode to output Port 2

CSSEL_OVR_EN

Chip select selector override enable

0 (B_0x0): CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are ignored, the chip select signals from OCTOSPIs or XSPIs are transmitted unconditionally

1 (B_0x1): CSSEL_OVR_O1 and CSSEL_OVR_O2 bit values are taken into account

CSSEL_OVR_O1

Chip select selector override setting for XSPI1

0 (B_0x0): XSPI1 can only use NCS1 (accesses using NCS2 are ignored)

1 (B_0x1): XSPI1 can only use NCS2 (accesses using NCS1 are ignored)

CSSEL_OVR_O2

Chip select selector override setting for XSPI2

0 (B_0x0): XSPI2 can only use NCS1 (accesses using NCS2 are ignored)

1 (B_0x1): XSPI2 can only use NCS2 (accesses using NCS1 are ignored)

REQ2ACK_TIME

REQ to ACK time

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