DBG_STOP=B_0x0, DBG_SLEEP=B_0x0, HLT_TSGEN_EN=B_0x0, DBG_STANDBY=B_0x0, TRACECLKEN=B_0x0, DBTRGOEN=B_0x0, DBGCLKEN=B_0x0
DBGMCU configuration register
| DBG_SLEEP | Allow debug in Sleep mode 0 (B_0x0): Normal operation. Peripheral clock are stopped automatically in Sleep mode 1 (B_0x1): Automatic clock stop disabled. Peripheral clock continues to run, allowing full debug capability. |
| DBG_STOP | Allow debug in Stop mode 0 (B_0x0): Normal operation. All clocks are disabled automatically in Stop mode 1 (B_0x1): Automatic clock stop disabled. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability. |
| DBG_STANDBY | Allow debug in Standby mode 0 (B_0x0): Normal operation. All clocks are disabled and the Vless thansub>DDless than/sub> domain powered down automatically in Standby mode. 1 (B_0x1): Automatic clock stop/power down disabled. All active clocks and oscillators continue to run during Standby mode, and the Vless thansub>DDless than/sub> domain supply is maintained, allowing full debug capability. |
| DBGCLKEN | Debug clock enable through software 0 (B_0x0): Debug clock is off. 1 (B_0x1): Debug clock is on. |
| TRACECLKEN | TPIU export clock enable through software 0 (B_0x0): TPIU clock is off. 1 (B_0x1): TPIU clock is on. |
| DBTRGOEN | DBTRGIO connection control 0 (B_0x0): DBTRGIO connected to DBTRGIN 1 (B_0x1): DBTRGIO connected to DBTRGOUT |
| HLT_TSGEN_EN | TSGEN halt enable 0 (B_0x0): TSGEN keeps on counting when processor is in halt. 1 (B_0x1): TSGEN stops counting when processor is in halt. |