GSI=B_0x0, MS=B_0x0, EL=B_0x0, WGTD=B_0x0, GFI=B_0x0, AWE=B_0x0, QCS=B_0x0, WECS=B_0x0, WFE=B_0x0, QGTP=B_0x0, SPL=B_0x0, SYS=B_0x0
FDCAN TT operation status register
| EL | Error level 0 (B_0x0): Severity 0 - No error 1 (B_0x1): Severity 1 - Warning 2 (B_0x2): Severity 2 - error 3 (B_0x3): Severity 3 - Severe error |
| MS | Master state 0 (B_0x0): Master_Off, no master properties relevant 1 (B_0x1): Operating as time Slave 2 (B_0x2): Operating as backup time master 3 (B_0x3): Operating as current time master |
| SYS | Synchronization state 0 (B_0x0): Out of Synchronization 1 (B_0x1): Synchronizing to FDCAN communication 2 (B_0x2): Schedule suspended by gap (In_Gap) 3 (B_0x3): Synchronized to schedule (In_Schedule) |
| QGTP | Quality of global time phase 0 (B_0x0): Global time not valid 1 (B_0x1): Global time in phase with time master |
| QCS | Quality of clock speed 0 (B_0x0): Local clock speed not synchronized to time master clock speed 1 (B_0x1): Synchronization deviation less than or equal to SDL |
| RTO | Reference trigger offset |
| WGTD | Wait for global time discontinuity 0 (B_0x0): No global time preset pending 1 (B_0x1): Node waits for the global time preset to take effect. The bit is reset when the node has transmitted a reference message with Disc_Bit = 1 or after it received a reference message. |
| GFI | Gap finished indicator 0 (B_0x0): Reset at the end of each reference message 1 (B_0x1): Gap finished by FDCAN |
| TMP | Time master priority |
| GSI | Gap started indicator 0 (B_0x0): No gap in schedule, reset by each reference message and for all time slaves 1 (B_0x1): Gap time after basic cycle has started |
| WFE | Wait for event 0 (B_0x0): No gap announced, reset by a reference message with Next_is_Gap = 0 1 (B_0x1): Reference message with Next_is_Gap = 1 received |
| AWE | Application watchdog event 0 (B_0x0): Application watchdog served in time 1 (B_0x1): Failed to serve application watchdog in time |
| WECS | Wait for external clock synchronization. 0 (B_0x0): No external clock synchronization pending 1 (B_0x1): Node waits for external clock synchronization to take effect. The bit is reset at the start of the next basic cycle. |
| SPL | Schedule phase lock 0 (B_0x0): Phase outside range 1 (B_0x1): Phase inside range |