SMBDEN=B_0x0, ALERTEN=B_0x0, ADDRACLR=B_0x0, DNF=B_0x0, SMBHEN=B_0x0, FMP=B_0x0, WUPEN=B_0x0, TXDMAEN=B_0x0, STOPIE=B_0x0, ERRIE=B_0x0, ADDRIE=B_0x0, NOSTRETCH=B_0x0, TXIE=B_0x0, PE=B_0x0, TCIE=B_0x0, SBC=B_0x0, ANFOFF=B_0x0, NACKIE=B_0x0, RXDMAEN=B_0x0, RXIE=B_0x0, STOPFACLR=B_0x0, PECEN=B_0x0, GCEN=B_0x0
I2C control register 1
| PE | Peripheral enable 0 (B_0x0): Peripheral disable 1 (B_0x1): Peripheral enable |
| TXIE | TX Interrupt enable 0 (B_0x0): Transmit (TXIS) interrupt disabled 1 (B_0x1): Transmit (TXIS) interrupt enabled |
| RXIE | RX Interrupt enable 0 (B_0x0): Receive (RXNE) interrupt disabled 1 (B_0x1): Receive (RXNE) interrupt enabled |
| ADDRIE | Address match Interrupt enable (slave only) 0 (B_0x0): Address match (ADDR) interrupts disabled 1 (B_0x1): Address match (ADDR) interrupts enabled |
| NACKIE | Not acknowledge received Interrupt enable 0 (B_0x0): Not acknowledge (NACKF) received interrupts disabled 1 (B_0x1): Not acknowledge (NACKF) received interrupts enabled |
| STOPIE | Stop detection Interrupt enable 0 (B_0x0): Stop detection (STOPF) interrupt disabled 1 (B_0x1): Stop detection (STOPF) interrupt enabled |
| TCIE | Transfer Complete interrupt enable 0 (B_0x0): Transfer Complete interrupt disabled 1 (B_0x1): Transfer Complete interrupt enabled |
| ERRIE | Error interrupts enable 0 (B_0x0): Error detection interrupts disabled 1 (B_0x1): Error detection interrupts enabled |
| DNF | Digital noise filter 0 (B_0x0): Digital filter disabled 1 (B_0x1): Digital filter enabled and filtering capability up to 1 tless thansub>I2CCLKless than/sub> 15 (B_0xF): digital filter enabled and filtering capability up to15 tless thansub>I2CCLKless than/sub> |
| ANFOFF | Analog noise filter OFF 0 (B_0x0): Analog noise filter enabled 1 (B_0x1): Analog noise filter disabled |
| TXDMAEN | DMA transmission requests enable 0 (B_0x0): DMA mode disabled for transmission 1 (B_0x1): DMA mode enabled for transmission |
| RXDMAEN | DMA reception requests enable 0 (B_0x0): DMA mode disabled for reception 1 (B_0x1): DMA mode enabled for reception |
| SBC | Slave byte control 0 (B_0x0): Slave byte control disabled 1 (B_0x1): Slave byte control enabled |
| NOSTRETCH | Clock stretching disable 0 (B_0x0): Clock stretching enabled 1 (B_0x1): Clock stretching disabled |
| WUPEN | Wakeup from Stop mode enable 0 (B_0x0): Wakeup from Stop mode disable. 1 (B_0x1): Wakeup from Stop mode enable. |
| GCEN | General call enable 0 (B_0x0): General call disabled. Address 0b00000000 is NACKed. 1 (B_0x1): General call enabled. Address 0b00000000 is ACKed. |
| SMBHEN | SMBus host address enable 0 (B_0x0): Host address disabled. Address 0b0001000x is NACKed. 1 (B_0x1): Host address enabled. Address 0b0001000x is ACKed. |
| SMBDEN | SMBus device default address enable 0 (B_0x0): Device default address disabled. Address 0b1100001x is NACKed. 1 (B_0x1): Device default address enabled. Address 0b1100001x is ACKed. |
| ALERTEN | SMBus alert enable 0 (B_0x0): The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). 1 (B_0x1): The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). |
| PECEN | PEC enable 0 (B_0x0): PEC calculation disabled 1 (B_0x1): PEC calculation enabled |
| FMP | Fast-mode Plus 20 mA drive enable 0 (B_0x0): 20 mA I/O drive disabled 1 (B_0x1): 20 mA I/O drive enabled |
| ADDRACLR | Address match flag (ADDR) automatic clear 0 (B_0x0): ADDR flag is set by hardware and cleared by software by setting ADDRCF bit. 1 (B_0x1): ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral. |
| STOPFACLR | STOP detection flag (STOPF) automatic clear 0 (B_0x0): STOPF flag is set by hardware and cleared by software by setting STOPCF bit. 1 (B_0x1): STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral. |