DATAINV=B_0x0, MSBFIRST=B_0x0, TXINV=B_0x0, SWAP=B_0x0, RXINV=B_0x0, ADDM7=B_0x0, STOP=B_0x0
LPUART control register 2
| ADDM7 | 7-bit Address Detection/4-bit Address Detection 0 (B_0x0): 4-bit address detection 1 (B_0x1): 7-bit address detection (in 8-bit data mode) |
| STOP | STOP bits 0 (B_0x0): 1 stop bit 2 (B_0x2): 2 stop bits |
| SWAP | Swap TX/RX pins 0 (B_0x0): TX/RX pins are used as defined in standard pinout 1 (B_0x1): The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. |
| RXINV | RX pin active level inversion 0 (B_0x0): RX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) 1 (B_0x1): RX pin signal values are inverted. ((Vless thansub>DDless than/sub> =0/mark, Gnd=1/idle). |
| TXINV | TX pin active level inversion 0 (B_0x0): TX pin signal works using the standard logic levels (Vless thansub>DDless than/sub> =1/idle, Gnd=0/mark) 1 (B_0x1): TX pin signal values are inverted. ((Vless thansub>DDless than/sub> =0/mark, Gnd=1/idle). |
| DATAINV | Binary data inversion 0 (B_0x0): Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1 (B_0x1): Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. |
| MSBFIRST | Most significant bit first 0 (B_0x0): data is transmitted/received with data bit 0 first, following the start bit. 1 (B_0x1): data is transmitted/received with the MSB (bit 7/8) first, following the start bit. |
| ADD | Address of the LPUART node |