stm32 /stm32n6 /STM32N647 /TIM4 /TIM4_CCMR1_OUTPUT

Capture/Compare 1 selection

0 (B_0x0): CC1 channel is configured as output.

1 (B_0x1): CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1.

2 (B_0x2): CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2.

3 (B_0x3): CC1 channel is configured as input, tim_ic1 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Output compare 1 fast enable

0 (B_0x0): CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.

1 (B_0x1): An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

Output compare 1 preload enable

0 (B_0x0): Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

1 (B_0x1): Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

OC1M[2:0]: Output compare 1 mode

0 (B_0x0): Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. This mode can be used when the timer serves as a software timebase. When the frozen mode is enabled during timer operation, the ouput keeps the state (active or inactive) it had before entering the frozen state.

1 (B_0x1): Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

2 (B_0x2): Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

3 (B_0x3): Toggle - tim_oc1ref toggles when TIMx_CNT=TIMx_CCR1.

4 (B_0x4): Force inactive level - tim_oc1ref is forced low.

5 (B_0x5): Force active level - tim_oc1ref is forced high.

6 (B_0x6): PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (tim_oc1ref=0) as long as TIMx_CNT>TIMx_CCR1 else active (tim_oc1ref=1).

7 (B_0x7): PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.

Output compare 1 clear enable

0 (B_0x0): tim_oc1ref is not affected by the tim_ocref_clr_int input

1 (B_0x1): tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int input

Capture/Compare 2 selection

0 (B_0x0): CC2 channel is configured as output

1 (B_0x1): CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2

2 (B_0x2): CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1

3 (B_0x3): CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)

Output compare 2 fast enable

Output compare 2 preload enable

OC2M[2:0]: Output compare 2 mode

Output compare 2 clear enable

OC1M[3]

OC2M[3]