stm32 /stm32n6 /STM32N655 /CRYP /CRYP_MISR

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Interpret as CRYP_MISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)INMIS 0 (B_0x0)OUTMIS

OUTMIS=B_0x0, INMIS=B_0x0

Description

CRYP masked interrupt status register

Fields

INMIS

Input FIFO service masked interrupt status

0 (B_0x0): No input FIFO event detected or INIM mask cleared in CRYP_IMSCR or CRYPEN bit cleared.

1 (B_0x1): Input FIFO empty or not full detected, with an interrupt pending

OUTMIS

Output FIFO service masked interrupt status

0 (B_0x0): No output FIFO event detected or OUTIM mask cleared in CRYP_IMSCR

1 (B_0x1): Output FIFO full or not empty detected, with an interrupt pending

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