MUXEN=B_0x0, WAITEN=B_0x0, CSCOUNT1=B_0x0, MBKEN=B_0x0, EXTMOD=B_0x0, CBURSTRW=B_0x0, MWID=B_0x0, FACCEN=B_0x0, WAITCFG=B_0x0, ASYNCWAIT=B_0x0, BURSTEN=B_0x0, CPSIZE=B_0x0, NBLSET=B_0x0, WREN=B_0x0, CSCOUNT0=B_0x0, WAITPOL=B_0x0, MTYP=B_0x0
SRAM/NOR Flash chip-select control register for memory region 2
| MBKEN | Memory region enable bit 0 (B_0x0): Corresponding memory region is disabled 1 (B_0x1): Corresponding memory region is enabled |
| MUXEN | Address/data multiplexing enable bit 0 (B_0x0): Address/Data non-multiplexed 1 (B_0x1): Address/Data multiplexed on databus (default after reset) |
| MTYP | Memory type 0 (B_0x0): SRAM/ FRAM (default after reset for memory region 2…4) 1 (B_0x1): PSRAM (CRAM)/FRAM 2 (B_0x2): NOR Flash/OneNAND Flash (default after reset for memory region 1) |
| MWID | Memory data bus width 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits (default after reset) 2 (B_0x2): 32 bits |
| FACCEN | Flash memory access enable 0 (B_0x0): Corresponding NOR Flash memory access is disabled 1 (B_0x1): Corresponding NOR Flash memory access is enabled (default after reset) |
| BURSTEN | Burst enable bit 0 (B_0x0): Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. 1 (B_0x1): Burst mode enable. Read accesses are performed in synchronous mode. |
| WAITPOL | Wait signal polarity bit 0 (B_0x0): NWAIT active low (default after reset), 1 (B_0x1): NWAIT active high. |
| WAITCFG | Wait timing configuration 0 (B_0x0): NWAIT signal active one data cycle before wait state (default after reset), 1 (B_0x1): NWAIT signal active during wait state (not used for PSRAM). |
| WREN | Write enable bit 0 (B_0x0): Write operations to the memory region by the FMC disabled. An AXI slave error is reported, 1 (B_0x1): Write operations to the memory region by the FMC enabled (default after reset). |
| WAITEN | Wait enable bit 0 (B_0x0): NWAIT signal disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period) 1 (B_0x1): NWAIT signal enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset) |
| EXTMOD | Extended mode enable 0 (B_0x0): Values inside FMC_BWTR register not taken into account (default after reset) 1 (B_0x1): Values inside FMC_BWTR register taken into account |
| ASYNCWAIT | Wait signal during asynchronous transfers 0 (B_0x0): NWAIT signal not taken in to account during asynchronous transfers (default after reset) 1 (B_0x1): NWAIT signal taken in to account during asynchronous transfers |
| CPSIZE | CRAM page size 0 (B_0x0): No burst split when crossing page boundary. (default after reset). 1 (B_0x1): 128 bytes 2 (B_0x2): 256 bytes 3 (B_0x3): 512 bytes 4 (B_0x4): 1024 bytes |
| CBURSTRW | Write burst enable 0 (B_0x0): Write operations are always performed in asynchronous mode 1 (B_0x1): Write operations are performed in synchronous mode. |
| CSCOUNT0 | Chip Select (CS) counter 0 (B_0x0): Counter disabled 1 (B_0x1): NEx deasserted after fmc_ker_ck clock cycle |
| CSCOUNT1 | Chip Select (CS) counter 0 (B_0x0): Counter disabled 1 (B_0x1): NEx deasserted after fmc_ker_ck clock cycle |
| NBLSET | Byte lane (NBL) setup 0 (B_0x0): NBL setup time is 0 fmc_ker_ck clock cycle. 1 (B_0x1): NBL setup time is 1 fmc_ker_ck clock cycle. 2 (B_0x2): NBL setup time is 2 fmc_ker_ck clock cycles. 3 (B_0x3): NBL setup time is 3 fmc_ker_ck clock cycles. |