stm32 /stm32n6 /STM32N655 /OTG1 /OTG_HCFG

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Interpret as OTG_HCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FSLSPCS 0 (FSLSS)FSLSS

Description

OTG host configuration register

Fields

FSLSPCS

FS/LS PHY clock select

1 (B_0x1_FS_HOST_MODE): PHY clock is running at 48 MHz

2 (B_0x2_LS_HOST_MODE): Select 6 MHz PHY clock frequency

FSLSS

FS- and LS-only support

Links

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