stm32 /stm32u0 /STM32U031 /EXTI /EXTI_EMR2

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Interpret as EXTI_EMR2

EM34=B_0x0, EM33=B_0x0, EM35=B_0x0, EM32=B_0x0, EM37=B_0x0, EM36=B_0x0

Description

EXTI CPU wake-up with event mask register

Fields

EM32	CPU wake-up with event generation mask on line x, (x1=1371to132) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked
EM33	CPU wake-up with event generation mask on line x, (x1=1371to132) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked
EM34	CPU wake-up with event generation mask on line x, (x1=1371to132) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked
EM35	CPU wake-up with event generation mask on line x, (x1=1371to132) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked
EM36	CPU wake-up with event generation mask on line x, (x1=1371to132) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked
EM37	CPU wake-up with event generation mask on line x, (x1=1371to132) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked

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